Modern microprocessor-based systems rely on memories for their operation in order to store programs and data for processing. As microprocessor-based systems become more sophisticated, larger memories are required. While larger memories are required, it is also desirable to have memories which are small in size and easy to manufacture. One popular type of memory array is a dynamic random access memory (DRAM) in which memory cells retain information only temporarily and must be refreshed at periodic intervals. Despite this limitation, DRAMs are widely used because they provide low cost per bit, high device density and feasibility of use.
In a DRAM, each memory cell typically includes an access transistor coupled to a storage capacitor. The memory cells are accessed by a series of intersecting word and bit lines connected to the access transistor. Word lines control the access transistors to allow the bit lines to read data into and out of the storage capacitors. In a conventional memory cell, there are a plurality of bit line contacts spaced equally apart along the bit lines. Bit line contacts are the contacts between the bit line and the access transistor. Also spaced evenly apart either over or under a bit line are a plurality of storage nodes. This is where the actual charge is stored in a memory cell. Associated with these storage nodes is a storage node contact. A storage node contact is a contact between an access transistor and the storage node or storage capacitor. In a typical memory cell structure, storage node contacts are in line with each other as one moves from one adjacent bit line to another. However, storage nodes, which are typically oval or oblong in shape, are offset slightly as one moves from one bit line to a next adjacent bit line. This is due to the fact that if storage nodes were not offset, they could touch a bit line contact resulting in a short in the memory cell. The storage nodes themselves are typically oblong or oval because other shapes would risk touching storage nodes from adjacent bit lines also causing a short.
This arrangement leads to crowded cell structures. Crowded cell structures make it difficult to manufacture the memory cell. To alleviate this situation, it is possible to increase the number of exposures during lithography or increase the cell size. However, increasing the exposure time during lithography increases the length of time to manufacture the DRAM. Increasing the cell size will make the size of the chip larger. Both of these approaches lead to increased cost as well as inefficient memory structures.